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Product Family / Category Middleware Solution, RTA |
Product / Topic RTA-OSEK |
Type Manual / Technical Documentation |
Title RTA-OSEK V4.0.0 Port Data Sheet for the Renesas H8S with Renesas Compiler |
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RTA-OSEK V4.0.0 Port Data Sheet for the Renesas H8S with Renesas Compiler
Typical RTOS overheads (based on example 8-task application built with BCC1):
- 1648 bytes ROM
- 72 bytes RAM data
- 408 bytes RAM stack
- Category 2 ISR Latency: 52 CPU cycles
- OSEK-OS V2.2 Certified
Hardware Environment
RTA-OSEK supports all variants of the Renesas H8S family with H8S 2600 core.
Software Environment
The RTA-OSEK Component for the Renesas H8S was built using the following tools:
- Hitachi C compiler Version 4.0.3
- Hitachi Assembler Version 4.1
- Hitachi Optimizing Linker Version 7.1.05.003
Please contact ETAS for details about compatibility with newer versions of this compiler.
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English
PDF · 327.7 KB · 10/14/2009